这一段verilog代码的怎么解读

///////////////////// I2C Control Clock ////////////////////////// Clock Settingparameter CLK_Freq = 25_000000; //25 MHzparameter I2C_Freq = 10_000; //10 KHzreg [15:0] mI2C_CLK_DIV; //CLK DIVreg mI2C_CTRL_CLK; //I2C Control Clockalways@(posedge iCLK or negedge iRST_N)begin if(!iRST_N) begin mI2C_CLK_DIV <= 0; mI2C_CTRL_CLK <= 0; end else begin if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq)/2) mI2C_CLK_DIV <= mI2C_CLK_DIV + 1✀d1; else begin mI2C_CLK_DIV <= 0; mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK; end endend⼀⼀-------------------------------------reg i2c_en_r0, i2c_en_r1;always@(posedge iCLK or negedge iRST_N)begin if(!iRST_N) begin i2c_en_r0 <= 0; i2c_en_r1 <= 0; end else begin i2c_en_r0 <= mI2C_CTRL_CLK; i2c_en_r1 <= i2c_en_r0; endendwire i2c_negclk = (i2c_en_r1 & ~i2c_en_r0) ? 1✀b1 : 1✀b0; ⼀⼀negedge i2c_sclk transfer data